1. Field of the Invention
The present invention relates to a flash memory device. More particularly, the invention relates to a method of reading data from a flash memory device, which is capable of pre-charging bit lines in a standby state to minimize coupling capacitance between neighboring bit lines during the read operation in order to remove coupling noise.
This application claims the benefit of Korean Patent Application No. 10-2006-0108529, filed on Nov. 3, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices and non-volatile memory devices according to their ability to retain stored data in the absence of continuously applied power. The class of non-volatile memory devices includes electrically erasable and programmable read only memory (EEPROM).
EEPROM operates in several fundamental modes, including; a programming mode adapted to write data to the non-volatile memory cells, a read mode adapted to read data stored in the non-volatile memory cells, and an erase mode adapted to erase data stored in the non-volatile memory cells.
Flash memory is one type of EEPROM and performs its erase operation on a block by block or sector by sector basis. Contemporary flash memory is implemented as either NAND type flash memory in which cell transistors are arranged in series between bit lines and a ground terminal, or NOR type flash memory in which cell transistors are arranged in parallel between bit lines and the ground terminal. NAND type flash memory is generally unable to execute read and programming operations on a byte by byte basis, but provides high speed programming and erase operations as compared to NOR type flash memory.
A read operation within a NAND type flash memory is executed on a page by page basis. A page buffer circuit that senses a bit line voltage reads data from memory cells connected to a selected wordline in a selected block. The read data of the page buffer circuit is stored in latches included in the page buffer circuit and then output to data lines.
Each memory cell is defined as either an ON-cell (erased cell) and an OFF-cell (programmed cell) according to its programming state. An OFF-cell has a high threshold voltage due to the presence of electrons injected onto the floating gate of its constituent memory cell transistor. An ON-cell has a low threshold voltage because any electrons previously injected onto its floating gate are removed during an erase operation.
FIG. (FIG.) 1 is a flow chart illustrating a conventional method of reading data from a flash memory device. Referring to FIG. 1, bit lines are discharged to a ground voltage VSS in a standby state or an idle state before the read operation is executed (S101). When associated read and address commands are received, the read operation begins by establishing the address of a selected memory cell from which data is to be read on the basis of the received commands (S103).
Then, the bit line connected to the selected memory cell from which data will be read, referred to as the “selected bit line,” is pre-charged to a power supply voltage VDD, and a row decoder sets signal lines including the bit lines to a predetermined voltage for the read operation (S105). The operation of setting the signal lines including the bit lines to the predetermined voltage by the row decoder is well known in the art so a more detailed explanation is omitted here.
After the signal lines including the bit lines are set to the predetermined voltage by the row decoder such that the read operation may be executed, the selected bit line is developed according to whether the selected cell is an ON-cell or an OFF-cell (S107). Specifically, the voltage of the selected bit line is gradually decreased when the selected cell is an ON-cell and the voltage of the selected bit line is maintained constant at the power supply voltage VDD when the selected cell is an OFF-cell.
After the selected bit line is developed, a sense amplifier senses and amplifies the resulting voltage variation for the selected bit line (S109). The sensed and amplified data is transmitted to a data output circuit to complete the read operation. Here again, the operation of the sense amplifier and the data output circuit are well known in the art.
After the read operation is completed, the selected bit line is discharged to ground voltage VSS during a recovery operation so that the bit lines are all discharged (S111). Accordingly, the flash memory device is returned to the standby state or idle state (S113).
FIG. 2 is a graph comparing the developed voltage variations between an ON-cell and an OFF-cell that arise during the conventional method of reading data from a flash memory device. FIG. 3 is a related conceptual diagram illustrating the development of noise during the conventional read operation. This noise is caused by a coupling capacitance (region A in FIG. 3) between a selected bit line and adjacent bit lines.
In the flash memory device, a wordline is commonly connected to memory cells belonging to a memory block. Thus, the wordline connected to the selected memory cell not only activates the selected bit line but also unselected bit lines. Furthermore, the selected bit line and the unselected bit lines are all discharged to ground voltage VSS in the standby state. Accordingly, when the voltage of the selected bit line is sensed and amplified while the unselected bit lines are discharged to ground voltage VSS, the coupling capacitance between the selected bit line and adjacent unselected bit line causes the voltage apparent on the unselected bit line to increase in the direction of voltage VDD. This voltage increase on the unselected bit line acts as noise, potentially changing the programming state of a memory cell adjacent to the selected cell. Accordingly, when data is subsequently read from the adjacent memory cell, an erroneous programming state is detected (e.g., a previously programmed OFF-cell is read as an ON-cell).